This application relates to test system algorithmic pattern generators (APGs) for testing circuits, such as integrated-circuit (IC) devices, and more particularly to APGs useful for testing semiconductor embedded arrays and memories (hereinafter “embedded memories”).
Test systems for testing IC devices, such as microprocessors, have become increasingly sophisticated, among other reasons, due to an increase in the number and size of embedded memories found in them. The characterization and testing of these embedded memories play a major role in ensuring the performance of these IC devices.
Various different approaches currently exist for characterizing and testing embedded memories. One such approach is to incorporate a Memory Built In Self Test (MBIST) mechanism within the IC device to be tested. An MBIST typically has a limited repertory of test algorithm patterns available that can be used to test the embedded memories of the IC device. An Algorithmic Pattern Generator (APG) is another mechanism that may be used to characterize and test embedded memories. Typically, an APG is used to apply characterization and defect exposure test patterns to a device under test (DUT) in cases where the test system employs a Direct Access Test (DAT) feature that enables direct access to embedded memories for control and observation. For example, in such a test system, the DUT input and output pins generally are routed through internal paths to embedded memories, which are individually controllable as if they were stand-alone memory devices. An example of an APG used in such a test system is described in U.S. Pat. No. 5,883,905, entitled “Pattern Generator with Extended Register Programming,” which is incorporated by reference.
There are challenges in applying APG test patterns to embedded memories located within a DUT, especially when the DUT includes several such embedded memories. The characterization and testing of embedded memories usually require generating numerous test patterns for each embedded memory. However, differences between one embedded memory to another within a DUT can increase the number of test patterns that are necessary to characterize and test the embedded memories. An example of such a difference is that pipeline depth often varies from one embedded memory to another. This results in different latency delays, which is the difference between the data input's latency delay and the data output's latency delay of an embedded memory. To account for differing latency delays, the resulting number of APG test algorithm patterns is increased by a factor of the number of different latency delays between various embedded memories in the DUT.
The width of various embedded memories (e.g., 18, 22 and 108 bits wide) also may vary from one embedded memory to another because chip designers tend to optimize use of the silicon area in an IC and therefore usually limit embedded memories to their necessary (minimum) size. Because the width of the data path accessing the data inputs/outputs of these embedded memories is fixed (e.g., 16 and 32 bits wide), multiple accesses and the ability to handle the irregular data word size for each access are usually required. For example, if a particular embedded memory is 18 bits wide and the data path accessing the embedded memory is 16 bits wide, then two accesses are required, with the second access requiring masking of 14 bits, which are un-used. If the masked un-used data bits must be part of the APG test algorithm patterns, then the number of different data widths between various embedded memories will require different sets of APG test algorithm patterns.
The different latency delays and data access widths between various embedded memories may burden conventional test system hardware and software and may cause a significant increase in the time the test system takes to reconfigure between each successive embedded memory test. In addition, test pattern generation often requires a user of the test system to possess extensive knowledge of the test system and the DUT to create efficient test patterns.